Recently, there are semiconductor devices having a package-on-package (PoP) structure in which a plurality of semiconductor packages are stacked one on another.
A technical literature relating to this is exemplified by Japanese Laid-Open Patent Publication No. 2009-70965 (Patent Document 1), which discloses such a semiconductor device having a PoP structure.
When controller and memory packages are stacked in this PoP structure, in general, the lower package is constituted by a controller chip, while the upper package is constituted by a memory chip. The upper package is connected to the lower package at the periphery of the lower package board, and hence external terminals (bump electrodes) are arranged only on the periphery of the upper package board.
However, in the upper package having the external terminals arranged only on the periphery, it is difficult to establish linear connection from a bonding pad to a land in an area where bonding pads of the wiring board are arranged closely to each other (dense wiring area).
Therefore, a wire is led from a bonding pad on one surface of the wiring board toward a central part thereof, then led to the other surface of the wiring board through a through via, and connected to a land arranged on the periphery of the other surface. As a result, the wiring length of the wiring on the wiring board is increased.